Regviz

NXP Semiconductors /LPC11E6x /DMA /SRAMBASE

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SRAMBASE

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/LPC11E6x/DMA/SRAMBASE#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RESERVED0OFFSET

Description

SRAM address of the channel configuration table.

Fields

RESERVED

Reserved. Read value is undefined, only zero should be written.
OFFSET

Address of the beginning of the DMA descriptor table. The table must begin on a 1 kB boundary. Boundary needed for 18 channel DMA configuration: 512 bytes (bottom 9 bits = 0)

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data